Notice on soliciting topics in the field of special integrated circuits for new generation information and communication technology innovation in 2022
In order to promote the scientific and technological innovation and industrial development of integrated circuits in our city, we are now openly soliciting topics in the field of integrated circuits in 2022 for innovative subjects in this city. In 2022, it is planned to collect projects in three directions, such as computing chips, analog chips and EDA tools in the field of integrated circuits, and it is planned to support 10 projects, and it is planned to arrange the municipal financial science and technology funds of 42 million yuan. The subject is declared in accordance with the research direction of the second-level title of the guide (such as 1. Energy-efficient in-memory computing chip). In 2022, the specific guidance directions and reporting requirements in the field of integrated circuits are as follows:
First, the direction of collection
(A) a new architecture computing chip
1. Energy-efficient in-memory computing chip
In order to meet the needs of the Internet of Things, mobile terminals, intelligent unmanned systems and other scenarios for energy-efficient computing, and to solve a series of problems such as "power wall" and "memory wall" in the existing computing architecture, in-memory computing chips based on traditional or new storage devices are developed. Study the in-memory computing unit and its process realization, study the new in-memory computing architecture and key technologies of the system, study the optimal deployment and reconfigurable architecture technology of core typical neural networks based on in-memory computing, and deploy application verification for typical intelligent processing scenarios such as audio and video.
2. Highly integrated memory and computing integrated chip
To meet the different requirements of the Internet of Things, intelligent unmanned systems, autonomous driving and other systems for the intelligence, miniaturization, low power consumption and low delay of visual sensors, a highly integrated and energy-efficient system on a chip integrating visual sensing, storage and computing is developed. This paper studies the circuit technology and the joint optimization method of software and hardware to realize sensing signal processing in analog and mixed signal domain. Develop an algorithm for typical intelligent visual perception scenes; Complete the application verification of intelligent visual perception scene for ultra-low power consumption and ultra-high speed requirements.
(2) High-end analog chips
3. High-precision ADC chip
Aiming at the urgent demand for high-precision measurement of analog parameters (such as voltage, current, temperature, pressure, etc.) in intelligent manufacturing, test equipment, instrumentation and other application scenarios, a high-precision ADC chip is developed. Study the design technology of ADC chip with high linearity, low temperature drift, low noise and low power consumption; Research on digital aided analog circuit design technology and high precision device mismatch error calibration technology; The design technology of analog front-end circuit with high signal-to-noise ratio and low harmonic distortion is studied. Complete the functional verification for typical industrial measurement and control scenarios.
4. High performance clock chip
Facing the urgent need of high-performance clock time synchronization chip for high-speed data transmission of data center, communication and Internet of Things equipment, a system-level clock chip suitable for clock time synchronization of various industries, such as synchronous timing, high-precision time synchronization and low-jitter arbitrary frequency generation, is developed. Research on intelligent algorithm control time-frequency synchronization chip system architecture; Research on low jitter clock jitter filtering PLL technology, high performance fractional frequency division technology and high precision time error detection technology; Complete application verification or large-scale commercialization for typical scenarios.
5. Ultra-high definition long-distance HDMI transmission chip
Aiming at the urgent need of high-speed and low-power data transmission for ultra-high definition long-distance transmission, an HDMI2.1 transmission chip with 48Gbps transmission rate is developed. Research on low-power ultra-high definition video transmitter and ultra-high bandwidth adaptive equalization video receiver; The phase-locked loop technology of low jitter clock and spread spectrum clock, and the generation technology of arbitrary fractional clock based on phase interpolation are studied. Study the real-time bidirectional transmission technology of ultra-high definition video; Research audio embedding extraction and video compression technology; Realize large-scale commercialization of long-distance network cable and optical fiber real-time bidirectional transmission for ultra-high-definition video.
6. Ultra-high-speed low-power interface chip
Facing the urgent demand for high-density, low-power consumption and high-reliability data transmission in high-performance computing and data centers, an ultra-high-speed Serdes chip with transmission rate of 100Gbps and above is developed. Research on high-speed and low-power data serialization driving transmission and reception links; The multi-phase ultra-low jitter clock generation circuit and clock phase calibration technology, receiver equalization technology and high-speed interface broadband impedance matching technology are studied. Combined with the specific protocol layer to form a standard chip to complete the application verification of typical scenarios.
(3) EDA tools
7. General parametric layout unit design software
Aiming at the advanced integrated circuit manufacturing process, the general parametric layout unit design software is developed. Study the general description language of parameterized layout unit; The efficient syntax analysis and abstract syntax tree optimization technology of general description language are studied, and the automatic generation technology from virtual layout unit to target layout unit is studied. The reusable high-performance function library of virtual layout unit for complex analog devices is studied. Study the visual editing and debugging technology of virtual layout unit; Study the DRC real-time verification technology of virtual layout unit; Complete the application verification for the back-end layout design requirements.
8. Integrated EDA tools for integrated circuit testing
In order to meet the urgent demand of EDA tools for automatic test circuit design to ensure chip quality in integrated circuit design process, an integrated EDA tool for integrated circuit test is developed, which integrates testability design, test generation and fault diagnosis. The method of generating test vectors for logic circuits that support both high fault coverage and high fault discrimination rate is studied, and the high parallel fault simulation technology is studied. Research the testability design method that supports fault testing and fault diagnosis at the same time, and study the logic circuit diagnosis method for multiple faults; Complete the application verification and commercial application of test integrated EDA tools in the design of domestic processor chips.
9. Analog circuit parasitic parameter extraction and analysis platform
Aiming at the demand of parasitic parameter extraction and analysis of high-end process analog circuits, a tool platform for parasitic parameter extraction and analysis of analog circuits is developed. The influence of various parasitic effects, including etch effect, CMP effect and raised diffusion structure, on parasitic parameters under high-end technology is studied. The accurate and fast algorithm for extracting parasitic parameters at the chip level is studied. Research on parallel extraction algorithm supporting multi-machine mode; Research on large-scale parasitic parameter analysis technology based on parasitic netlist; Complete the application verification of the chip-level analog circuit parasitic parameter extraction and analysis tool in the actual analog circuit chip design.
10. Power supply integrity simulation analysis and diagnosis platform
There is an urgent need for power integrity analysis for multi-scale advanced packaging design, and an efficient and high-precision power integrity simulation analysis and diagnosis platform is developed. This paper studies the polygon alignment and simplified processing technology and field identification technology of multi-layer VLSI layout from centimeter level to nanometer level. Study the grid generation platform of multi-scale structure of system-level advanced packaging structure; The parallel solution technology of ultra-large sparse matrix for solving the field is studied. Study the error diagnosis technology of advanced packaging design layout; Achieve high-efficiency and high-precision simulation and diagnosis of advanced packaged power supply integrity analysis.
Second, the support amount and cycle
Fixed funding, the first and second projects are supported by 5 million yuan, and other projects are supported by 4 million yuan. The research content of the subject must cover all the contents listed in the corresponding sub-direction. The project implementation period is generally 2 years, not more than 3 years.
Third, the reporting requirements
1. The application subject should have a clear technical route, strong industrial traction, contribution and social benefits, and clear and quantifiable objectives and assessment indicators.
2. The applicant shall be an enterprise or institution registered in Beijing with independent legal personality, with corresponding scientific research capabilities and conditions and standardized operation and management. Encourage enterprises to take the lead, and Industry-University-Research should use combination.
3. The applicant and the person in charge of the application shall comply with the requirements of the Measures for the Administration of Beijing Science and Technology Plan Projects (Projects) and the Measures for the Credit Management of Relevant Responsible Subjects in Beijing Science and Technology Plan Management; There is no bad credit record in applying for various scientific research projects (topics) at all levels in the past 3 years. No administrative punishment or illegal record, no bad scientific research integrity record.
4. If the applicant is an enterprise, in principle, it can participate in no more than one special declaration. The total investment and source of funds of the project should be clearly stated, and corresponding matching funds should be provided. The ratio of matching funds to science and technology funds should not be less than 2:1.
5. In principle, the person in charge of the declaration shall undertake no more than 2 projects (projects) of Beijing Science and Technology Plan as the person in charge, and the number of projects as the main participants shall not exceed 3 in principle.
Fourth, the declaration method
1. Take the online declaration method. After the applicant logs in to the "Beijing Science and Technology Plan Integrated Management Platform-Online Service System" (https://mis.kw.beijing.gov.cn/) through the legal person’s one-card pass to update the information of the applicant, the applicant logs in to the system and binds the applicant, selects the corresponding application type, completes the report of the implementation plan, and uploads the summary of the project (see the annex, the summary of the situation and the assessment indicators are no more than two pages) and other supporting materials required for the application of the project.
2. The scientific research department of the reporting unit is responsible for reviewing the online reporting scheme, submitting it uniformly within the reporting time limit, downloading and printing the reporting list, affixing the official seal of the unit in duplicate, scanning it into a PDF file and uploading it to the system.
3. The deadline for project application and acceptance is 24:00 on August 28th, 2022, when the system will automatically shut down.
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Attachment: Summary of topics
Beijing Municipal Science and Technology Commission, Zhongguancun Science Park Management Committee
August 5, 2022